Register CheatSheet

This will be a resume of all the registers that I use.  You can use this page as a quick reference.
This is copied from the appropriate user manual or data sheet

It is a work in progress.  I will put some JavaScript to have sort of a tree to only show the information you want.  Its suppose to be a quick reference.

ADC status register (ADC_SR)
Bit 4 STRT: Regular channel Start flag
Bit 3 JSTRT: Injected channel Start flag
Bit 2 JEOC: Injected channel end of conversion
Bit 1 EOC: End of conversion
Bit 0 AWD: Analog watchdog flag

ADC control register 1 (ADC_CR1)
Bit 23 AWDEN: Analog watchdog enable on regular channels
Bit 22 JAWDEN: Analog watchdog enable on injected channels
Bits 19:16 DUALMOD[3:0]: Dual mode selection
0000: Independent mode.
0001: Combined regular simultaneous + injected simultaneous mode
0010: Combined regular simultaneous + alternate trigger mode
0011: Combined injected simultaneous + fast interleaved mode
0100: Combined injected simultaneous + slow Interleaved mode
0101: Injected simultaneous mode only
0110: Regular simultaneous mode only
0111: Fast interleaved mode only
1000: Slow interleaved mode only
1001: Alternate trigger mode only
Bits 15:13 DISCNUM[2:0]: Discontinuous mode channel count 0 being 1 channel
Bit 12 JDISCEN: Discontinuous mode on injected channels
Bit 11 DISCEN: Discontinuous mode on regular channels
Bit 10 JAUTO: Automatic Injected Group conversion
Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode
Bit 8 SCAN: Scan mode
Bit 7 JEOCIE: Interrupt enable for injected channels
Bit 6 AWDIE: Analog watchdog interrupt enable
Bit 5 EOCIE: Interrupt enable for EOC
Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits